I. Field of the Invention
This invention relates generally to packaging of electronic components, and more particularly to a way of effecting overall volumetric efficiency resulting in significant size reduction while still maintaining the requirement for electrically conductive pathways for active components.
II. Discussion of the Prior Art
In the field of implantable medical devices, such as automatic implantable cardiac defibrillators, cardiac pacemakers, neural stimulators and the like, there has been an on-going effort to reduce the physical size of the implantable devices while continuing to increase the functional capabilities of such devices.
Referring to FIG. 1, prior art packaging arrangements used in such devices typically have hybrid circuits whose sizes, surface areas, and volumes are defined by the X-axis and Y-axis area consumed by the necessary electrical components that are populated in a planar format lying parallel to the main hybrid motherboard assembly. Typically, the Z-axis utilization is neglected, being determined strictly by the thickest (tallest) electrical component on the assembly. Thus, a need exists for a packaging arrangement that more effectively utilizes hybrid area and volume parameters to achieve an overall device size reduction.